In response to a desire for faster, more efficient computer processing systems, attention has been directed to increasing throughput at various levels of a computer system. For example, one level may comprise a memory system, wherein a processor may generate read or write requests at a rate faster than a memory system can handle. Accordingly, techniques for dealing with operating capability imbalances have led to development of multi-channel memory devices. Generally, a dual-channel memory device may incorporate two parallel channels to operate concurrently to reduce latency involving memory read/write operations, for example. In particular, a memory controller may transmit or receive addressed read or write instruction signals to or from multiple memory arrays via two separate, parallel channels. Similarly, two separate, host interfaces may be electronically connected to respective channels of a dual-channel memory device.